| KyteLabs AS80C52 CrossAssembler - Online User Manual | Last modified: 2005-03-04 (14366) |
; SFR.D 11536.C1 ** 4.6.1997
;-------------------------------------------------------------------------------
; Copyright (C) 1997 Kybertechnik Labor, Berlin.
;
; Special Function Registers
;
; An overview to all(?) derivatives of the 8051 family of microcontrollers.
; 1. Sorted by address.
; Address Register Name Function Resident in
;-------------------------------------------------------------------------------
; 80 P0 Port 0 8051
; Bits in P0:
; Bit address Name Function Resident in
; 80 P0.0 Parallel I/O Port 0 Bit 0 8051
; 80 P0.0 AD0 Multiplexed Address/Data Bit 0 8031
; 81 P0.1 Parallel I/O Port 0 Bit 1 8051
; 81 P0.1 AD1 Multiplexed Address/Data Bit 1 8031
; 82 P0.2 Parallel I/O Port 0 Bit 2 8051
; 82 P0.2 AD2 Multiplexed Address/Data Bit 2 8031
; 83 P0.3 Parallel I/O Port 0 Bit 3 8051
; 83 P0.3 AD3 Multiplexed Address/Data Bit 3 8031
; 84 P0.4 Parallel I/O Port 0 Bit 4 8051
; 84 P0.4 AD4 Multiplexed Address/Data Bit 4 8031
; 85 P0.5 Parallel I/O Port 0 Bit 5 8051
; 85 P0.5 AD5 Multiplexed Address/Data Bit 5 8031
; 86 P0.6 Parallel I/O Port 0 Bit 6 8051
; 83 P0.6 AD6 Multiplexed Address/Data Bit 6 8031
; 87 P0.7 Parallel I/O Port 0 Bit 7 8051
; 87 P0.7 AD3 Multiplexed Address/Data Bit 7 8031
;-------------------------------------------------------------------------------
; 81 SP Stack Pointer 8051
; 82 DPL Data Pointer Low Byte 8051
; 83 DPH Data Pointer High Byte 8051
;-------------------------------------------------------------------------------
; 84 ADRES0 A/D Conversion Result of Channel 0, ACH0-3 80C51GB
; 84 DPL1 Data Pointer 1 Low Byte 80C310
; 84 GMOD Global Serial Channel Mode 80C152
; 84 WDTL not user accessable 80C517A
; Bits in GMOD ( not bit-addressable ):
; 0 PR Protocol SDLC with NRZI 80C152
; 1 PL0 Preamble Length Bit 0 80C152
; 2 PL1 Preamble Length Bit 1 80C152
; 3 CT CRC Type 32-Bit AUTODIN-II-32 80C152
; 4 AL Address Length 16-Bit 80C152
; 5 M0 Mode Select Bit 0 80C152
; 6 M1 Mode Select Bit 1 80C152
; 7 XTCLK External Transmit Clock 80C152
;-------------------------------------------------------------------------------
; 85 DPH1 Data Pointer 1 High Byte 80C310
; 85 TFIFO Global Serial Channel Transmit Buffer 80C152
; 85 WDTH not user accessable 80C517A
;-------------------------------------------------------------------------------
; 86 DPS Data Pointer Select 80C310
; 86 WDTREL Watchdog Timer Reload Register 80C517
; Bits in WDTREL ( not bit-adressable ):
; 0 WDTREL0 Watchdog Timer Reload Value Bit 0 80C517
; 1 WDTREL1 Watchdog Timer Reload Value Bit 1 80C517
; 2 WDTREL2 Watchdog Timer Reload Value Bit 2 80C517
; 3 WDTREL3 Watchdog Timer Reload Value Bit 3 80C517
; 4 WDTREL4 Watchdog Timer Reload Value Bit 4 80C517
; 5 WDTREL5 Watchdog Timer Reload Value Bit 5 80C517
; 6 WDTREL6 Watchdog Timer Reload Value Bit 6 80C517
; 7 WDTREL7 Watchdog Timer Prescaler Select Bit (/16) 80C517
;-------------------------------------------------------------------------------
; 87 PCON Power Control 8051
; Bits in PCON ( not bit-addressable ):
; 0 IDL Idle Mode Select 80C51
; 0 IDLE Idle Mode Enable Bit 80C515
; 1 PD Power Down Bit 80C51
; 1 PDE Power-Down Enable Bit 80C515
; 1 STOP Stop Mode Select 80C310
; 2 GF0 General Purpose Flag Bit 0 80C51
; 2 GFIEN GSC Flag Idle Enable 80C152
; 3 GF1 General Purpose Flag Bit 1 80C51
; 3 XRCLK GSC External Receive Clock Enable 80C152
; 4 GAREN GSC Auxiliary Receiver Enable Bit 80C152
; 4 POF Power Off Flag 80C51FX
; 4 SD Enable Slow-Down Mode 80C517
; 5 IDLS Idle Start Bit 80C515
; 5 REQ Enable DMA Logic nHLD-Generate nHLDA-Detect 80C152/452
; 6 ARB Enable DMA Logic nHLD-Detect nHLDA-Generate 80C152/452
; 6 PDS Power-Down Start Bit 80C515
; 6 SMOD0 Serial Mode Framing Error Detection 80C52
; 7 SMOD Double Baudrate Bit 8051
; 7 SMOD1 Double Baudrate Bit 80C52
; 7 SMOD_0 Serial Port 0 Baudrate Doubler Enable 80C310
;-------------------------------------------------------------------------------
; 88 TCON Timer/Counter Control 8051
; Bits in TCON:
; Bit address Name Function Resident in
; 88 TCON.0 IT0 Interrupt 0 Type Control Bit 8051
; 89 TCON.1 IE0 External Interrupt 0 Edge Flag 8051
; 8A TCON.2 IT1 Interrupt 1 Type Control Bit 8051
; 8B TCON.3 IE1 External Interrupt 1 Edge Flag 8051
; 8C TCON.4 TR0 Timer 0 Run Control Bit 8051
; 8D TCON.5 TF0 Timer 0 Overflow Flag 8051
; 8E TCON.6 TR1 Timer 1 Run Control Bit 8051
; 8F TCON.7 TF1 Timer 1 Overflow Flag 8051
;-------------------------------------------------------------------------------
; 89 TMOD Timer/Counter Mode Control 8051
; Bits in TMOD ( not bit-adressable ):
; 0 M0T0 Mode Selector Bit 0 Timer 0 8051
; 1 M1T0 Mode Selector Bit 1 Timer 0 8051
; 2 CNT0 Timer or Counter Selector Timer 0 8051
; 3 GATE0 Timer/Counter Gate Input Timer 0 8051
; 4 M0T1 Mode Selector Bit 0 Timer 1 8051
; 5 M1T1 Mode Selector Bit 1 Timer 1 8051
; 6 CNT1 Timer or Counter Selector Timer 1 8051
; 7 GATE1 Timer/Counter Gate Input Timer 1 8051
;-------------------------------------------------------------------------------
; 8A TL0 Timer/Counter 0 Low Byte 8051
; 8B TL1 Timer/Counter 1 Low Byte 8051
; 8C TH0 Timer/Counter 0 High Byte 8051
; 8D TH1 Timer/Counter 1 High Byte 8051
;-------------------------------------------------------------------------------
; 8E AUXR Auxiliary Register 80C54/58 80C51GB
; 8E CKCON Clock Control 80C310
; Bits in AUXR ( not bit-adressable ):
; 0 Disable ALE 80C54/58
; 0 RFI Enable RFI Reduction Mode 80C51GB
; 1
; 2
; 3
; 4
; 5
; 6
; 7
; Bits in CKCON ( not bit-adressable ):
; 0 MD0 Stretch MOVX Select Bit 0 80C310
; 1 MD1 Stretch MOVX Select Bit 1 80C310
; 2 MD2 Stretch MOVX Select Bit 2 80C310
; 3 T0M Timer 0 Clock Select 80C310
; 4 T1M Timer 1 Clock Select 80C310
; 5 T2M Timer 2 Clock Select 80C310
; 6 WD0 Watchdog Timer Mode Select Bit 0 80C320
; 7 WD1 Watchdog Timer Mode Select Bit 1 80C320
;-------------------------------------------------------------------------------
; 8F
;-------------------------------------------------------------------------------
; 90 P1 Port 1 8051
; Bits in P1:
; Bit address Name Function Resident in
; 90 P1.0 Parallel I/O Port 1 Bit 0 8051
; 90 P1.0 CC0 Compare 0 Output, Capture 0 Input (CRCL/H) 80515
; 90 P1.0 GRXD Global Serial Channel (GSC) Data Input 80C152
; 90 P1.0 nINT3 External Interrupt 3 Input 80515
; 90 P1.0 T2 Timer/Counter 2 External Input 8052 80C310
; 90 P1.0 T2 Timer/Counter 2 External Input/Clock Output 80C51FC
; 91 P1.1 Parallel I/O Port 1 Bit 1 8051
; 91 P1.1 CC1 Compare 1 Output, Capture 1 Input (CCL/H1) 80515
; 91 P1.1 GTXD Global Serial Channel (GSC) Data Output 80C152
; 91 P1.1 INT4 External Interrupt 4 Input 80515
; 91 P1.1 T2EX Timer/Counter 2 Capture/Reload Trigger 8052 80C310
; 91 P1.1 T2EX Timer/Counter 2 Capture/Reload/Direction 80C51GB
; 92 P1.2 Parallel I/O Port 1 Bit 2 8051
; 92 P1.2 C PCA External Clock Input 80C51GB
; 92 P1.2 CC2 Compare 2 Output, Capture 2 Input (CCL/H2) 80515
; 92 P1.2 ECI PCA External Clock Input 80C51FX
; 92 P1.2 INT5 External Interrupt 5 Input 80515
; 92 P1.2 nDEN GSC External Driver Enable 80C152
; 92 P1.2 RXD1 Serial Port 1 Receive 80C320
; 93 P1.3 Parallel I/O Port 1 Bit 3 8051
; 93 P1.3 CC3 Compare 3 Output, Capture 3 Input (CCL/H3) 80515
; 93 P1.3 CEX0 PCA 0 Capture Input, Compare/PWM Output 80C51FX
; 93 P1.3 nINT6 External Interrupt 6 Input 80515
; 93 P1.3 nTXC GSC External Transmit Clock Input 80C152
; 93 P1.3 TXD1 Serial Port 1 Transmit 80C320
; 94 P1.4 Parallel I/O Port 1 Bit 4 8051
; 94 P1.4 CEX1 PCA 1 Capture Input, Compare/PWM Output 80C51FX
; 94 P1.4 nINT2 External Interrupt 2 Input 80515
; 94 P1.4 nRXC GSC External Receive Clock Input 80C152
; 94 P1.4 INT2 External Interrupt 2 80C310
; 95 P1.5 Parallel I/O Port 1 Bit 5 8051
; 95 P1.5 CEX2 PCA 2 Capture Input, Compare/PWM Output 80C51FX
; 95 P1.5 nHLD DMA Hold Input/Output 80C152
; 95 P1.5 nINT3 External Interrupt 3 80C310
; 95 P1.5 T2EX Timer 2 External Reload Trigger Input 80515
; 96 P1.6 Parallel I/O Port 1 Bit 6 8051
; 96 P1.6 CEX3 PCA 3 Capture Input, Compare/PWM Output 80C51FX
; 96 P1.6 CLKOUT System Clock Output 80515
; 96 P1.6 INT4 External Interrupt 4 80C310
; 96 P1.6 nHLDA DMA Hold Acknowledge Input/Output 80C152
; 97 P1.7 Parallel I/O Port 1 Bit 7 8051
; 97 P1.7 CEX4 PCA 4 Capture Input, Compare/PWM Output 80C51FX
; 97 P1.7 nINT5 External Interrupt 5 80C310
; 95 P1.7 T2 Timer 2 External Count or Gate Input 80515
;-------------------------------------------------------------------------------
; 91 EXIF External Interrupt Flags 80C310
; 91 P5 Port 5 80C152
; 91 XPAGE Internal XRAM Page Register 80C517A
; Bits in EXIF ( not bit-adressable ):
; 0 BGS Band-Gap Select 80C320
; 1 RGSL Ring Oscillator Select 80C320
; 2 RGMD Ring Mode Status 80C320
; 3 XTnRG Crystal/Ring Source Select 87C520
; 4 IE2 External Interrupt 2 Flag 80C310
; 5 IE3 External Interrupt 3 Flag 80C310
; 6 IE4 External Interrupt 4 Flag 80C310
; 7 IE5 External Interrupt 5 Flag 80C310
;-------------------------------------------------------------------------------
; 92 DCON0 DMA Control 0 80C152/452
; 92 DPSEL Data Pointer Select Register 80C517
; Bits in DCON0 ( not bit-adressable ):
; 0 GO0 DMA Channel 0 Enable 80C152/452
; 1 DONE0 DMA Channel 0 Operation Done Flag 80C152/452
; 2 TM0 DMA Channel 0 Transfer Mode 80C152/452
; 3 DM0 DMA Channel 0 Demand Mode 80C152/452
; 4 ISA0 DMA Channel 0 Increment Source Address 80C152/452
; 5 SAS0 DMA Channel 0 Source Address Space 80C152/452
; 6 IDA0 DMA Channel 0 Increment Destination Address 80C152/452
; 7 DAS0 DMA Channel 0 Destination Address Space 80C152/452
;---------------------------------------------------------------------------
; 93 DCON1 DMA Control 1 80C152/452
; Bits in DCON1 ( not bit-adressable ):
; 0 GO1 DMA Channel 1 Enable 80C152/452
; 1 DONE1 DMA Channel 1 Operation Done Flag 80C152/452
; 2 TM1 DMA Channel 1 Transfer Mode 80C152/452
; 3 DM1 DMA Channel 1 Demand Mode 80C152/452
; 4 ISA1 DMA Channel 1 Increment Source Address 80C152/452
; 5 SAS1 DMA Channel 1 Source Address Space 80C152/452
; 6 IDA1 DMA Channel 1 Increment Destination Address 80C152/452
; 7 DAS1 DMA Channel 1 Destination Address Space 80C152/452
;-------------------------------------------------------------------------------
; 94 ADRES1 A/D Conversion Result of Channel 1, ACH0-3 80C51GB
; 94 BAUD Global Serial Channel Baud Rate 80C152
; 95 ADR0 Global Serial Channel Match Address 0 80C152
;-------------------------------------------------------------------------------
; 96 TRIM RTC Trim Register 87C530
; Bits in TRIM ( not bit-adressable ):
; 0 nTRM0 RTC Inverted Trim Bit 0 87C530
; 1 TRM0 RTC Trim Bit 0 87C530
; 2 nTRM1 RTC Inverted Trim Bit 1 87C530
; 3 TRM1 RTC Trim Bit 1 87C530
; 4 nTRM2 RTC Inverted Trim Bit 2 87C530
; 5 TRM2 RTC Trim Bit 2 87C530
; 6 X12n6 RTC Crystal Capacitance Select 87C530
; 7 E4K External RTC 4096Hz Signal Enable 87C530
;-------------------------------------------------------------------------------
; 97 ACON A/D Control Register 80C51GB
; Bits in ACON ( not bit-adressable ):
; 0 ATM A/D Trigger Mode 80C51GB
; 1 AIM A/D Input Mode 80C51GB
; 2 ACS0 A/D Channel Select Bit 0 80C51GB
; 3 ACS1 A/D Channel Select Bit 1 80C51GB
; 4 ACE A/D Conversion Enable 80C51GB
; 5 AIF A/D Interrupt Flag 80C51GB
; 6
; 7
;---------------------------------------------------------------------------
; 98 SCON Local Serial Channel Control 80C152
; 98 SCON Serial Control 8051
; Bits in SCON:
; Bit address Name Function Resident in
; 98 SCON.0 RI Receive Interrupt Flag 8051
; 99 SCON.1 TI Transmit Interrupt Flag 8051
; 9A SCON.2 RB8 Received 9th Data Bit 8051
; 9B SCON.3 TB8 9th Data Bit to Transmit 8051
; 9C SCON.4 REN Receive Enable 8051
; 9D SCON.5 SM2 Multiprocessor Communication Mode 8051
; 9E SCON.6 SM1 Serial Port Mode Specifier 1 8051
; 9F SCON.7 SM0 Serial Port Mode Specifier 0 8051
; 9F SCON.7 FE Framing Error Bit ( nur wenn SMOD0=1 ) 80C52
;-------------------------------------------------------------------------------
; 99 SBUF Local Serial Channel Buffer 80C152
; 99 SBUF Serial Data Buffer 8051
;-------------------------------------------------------------------------------
; 9A C1CAPM0 PCA1 Module Compare/Capture Register 0 80C51GB
; 9A IEN2 Interrupt Enable Register 2 80C517
; Bits in C1CAPM0 ( not bit-adressable ):
; 0 E1CCF0 Enable Compare/Capture Flag 0 Interrupt 80C51GB
; 1 PWM10 Pulse Width Modulation Mode on C1EX0 80C51GB
; 2 TOG10 Toggle on C1EX0 80C51GB
; 3 MAT10 Match Compare/Capture Register 0 80C51GB
; 4 CAP1N0 Capture Negative Edge on C1EX0 80C51GB
; 5 CAP1P0 Capture Positive Edge on C1EX0 80C51GB
; 6 E1COM0 Enable Comparator Register 0 80C51GB
; 7
; Bits in IEN2 ( not bit-adressable ):
; 0 ES1 Enable Serial Interrupt of Channel 1 80C517
; 1
; 2 ECMP Enable Compare Match Interrupt for CM0-7 80C517A
; 3 ECT Enable Compare Timer Interrupt 80C517
; 4 ECS Enable Compare Match Interrupt for COMSET 80C517A
; 5 ECR Enable Compare Match Interrupt for COMCLR 80C517A
; 6
; 7
;-------------------------------------------------------------------------------
; 9B C1CAPM1 PCA1 Module Compare/Capture Register 1 80C51GB
; 9B S1CON Serial Channel 1 Control Register 80C517
; Bits in C1CAPM1 ( not bit-adressable ):
; 0 E1CCF1 Enable Compare/Capture Flag 1 Interrupt 80C51GB
; 1 PWM11 Pulse Width Modulation Mode on C1EX1 80C51GB
; 2 TOG11 Toggle on C1EX1 80C51GB
; 3 MAT11 Match Compare/Capture Register 1 80C51GB
; 4 CAP1N1 Capture Negative Edge on C1EX1 80C51GB
; 5 CAP1P1 Capture Positive Edge on C1EX1 80C51GB
; 6 E1COM1 Enable Comparator Register 1 80C51GB
; 7
; Bits in S1CON ( not bit-adressable ):
; 0 RI1 Receiver Interrupt of Channel 1 80C517
; 1 TI1 Transmitter Interrupt of Channel 1 80C517
; 2 RB81 Receiver Bit 8 of Channel 1 80C517
; 3 TB81 Transmitter Bit 8 of Channel 1 80C517
; 4 REN1 Receiver Enable of Channel 1 80C517
; 5 SM21 Enable Multiprocessor Comm of Channel 1 80C517
; 6
; 7 SM Serial Mode 8-Bit UART 80C517
;-------------------------------------------------------------------------------
; 9C C1CAPM2 PCA1 Module Compare/Capture Register 2 80C51GB
; 9C S1BUF Serial Channel 1 Buffer Register 80C517
; Bits in C1CAPM2 ( not bit-adressable ):
; 0 E1CCF2 Enable Compare/Capture Flag 2 Interrupt 80C51GB
; 1 PWM12 Pulse Width Modulation Mode on C1EX2 80C51GB
; 2 TOG12 Toggle on C1EX2 80C51GB
; 3 MAT12 Match Compare/Capture Register 2 80C51GB
; 4 CAP1N2 Capture Negative Edge on C1EX2 80C51GB
; 5 CAP1P2 Capture Positive Edge on C1EX2 80C51GB
; 6 E1COM2 Enable Comparator Register 2 80C51GB
; 7
;-------------------------------------------------------------------------------
; 9D C1CAPM3 PCA1 Module Compare/Capture Register 3 80C51GB
; 9D S1RELL Baudrate 1 Timer Reload Value, Low Byte 80C517
; Bits in C1CAPM3 ( not bit-adressable ):
; 0 E1CCF3 Enable Compare/Capture Flag 3 Interrupt 80C51GB
; 1 PWM13 Pulse Width Modulation Mode on C1EX3 80C51GB
; 2 TOG13 Toggle on C1EX3 80C51GB
; 3 MAT13 Match Compare/Capture Register 3 80C51GB
; 4 CAP1N3 Capture Negative Edge on C1EX3 80C51GB
; 5 CAP1P3 Capture Positive Edge on C1EX3 80C51GB
; 6 E1COM3 Enable Comparator Register 3 80C51GB
; 7
;---------------------------------------------------------------------------
; 9E C1CAPM4 PCA1 Module Compare/Capture Register 4 80C51GB
; Bits in C1CAPM4 ( not bit-adressable ):
; 0 E1CCF4 Enable Compare/Capture Flag 4 Interrupt 80C51GB
; 1 PWM14 Pulse Width Modulation Mode on C1EX4 80C51GB
; 2 TOG14 Toggle on C1EX4 80C51GB
; 3 MAT14 Match Compare/Capture Register 4 80C51GB
; 4 CAP1N4 Capture Negative Edge on C1EX4 80C51GB
; 5 CAP1P4 Capture Positive Edge on C1EX4 80C51GB
; 6 E1COM4 Enable Comparator Register 4 80C51GB
; 7
;-------------------------------------------------------------------------------
; 9F C1MOD PCA1 Counter Mode Register 80C51GB
; Bits in C1MOD ( not bit-adressable ):
; 0 ECF1 PCA1 Enable Counter Overflow Interrupt 80C51GB
; 1 C1PS0 PCA1 Count Pulse Select Bit 0 80C51GB
; 2 C1PS1 PCA1 Count Pulse Select Bit 1 80C51GB
; 3 C1PS2 PCA1 Count Pulse Select Bit 2 80C51GB
; 4
; 5
; 6
; 7
;-------------------------------------------------------------------------------
; A0 P2 Port 2 8051
; Bits in P2:
; Bit address Name Function Resident in
; A0 P2.0 Parallel I/O Port 2 Bit 0 8051
; A0 P2.0 A8 Address Bit 8 8031
; A1 P2.1 Parallel I/O Port 2 Bit 1 8051
; A1 P2.1 A9 Address Bit 9 8031
; A2 P2.2 Parallel I/O Port 2 Bit 2 8051
; A2 P2.2 A10 Address Bit 10 8031
; A3 P2.3 Parallel I/O Port 2 Bit 3 8051
; A3 P2.3 A11 Address Bit 11 8031
; A4 P2.4 Parallel I/O Port 2 Bit 4 8051
; A4 P2.4 A12 Address Bit 12 8031
; A5 P2.5 Parallel I/O Port 2 Bit 5 8051
; A5 P2.5 A13 Address Bit 13 8031
; A6 P2.6 Parallel I/O Port 2 Bit 6 8051
; A6 P2.6 A14 Address Bit 14 8031
; A7 P2.7 Parallel I/O Port 2 Bit 7 8051
; A7 P2.7 A15 Address Bit 15 8031
;-------------------------------------------------------------------------------
; A1 COMSETL Compare Register COMSET, Low Byte 80C517A
; A1 P6 Port 6 80C152
; A2 COMSETH Compare Register COMSET, High Byte 80C517A
; A2 SARL0 DMA Source Address 0 (LOW) 80C152/452
; A3 COMCLRL Compare Register COMCLR, Low Byte 80C517A
; A3 SARH0 DMA Source Address 0 (HIGH) 80C152/452
; A4 ADRES2 A/D Conversion Result of Channel 2, ACH0-3 80C51GB
; A4 COMCLRH Compare Register COMCLR, High Byte 80C517A
; A4 IFS Global Serial Channel Interframe Spacing 80C152
;-------------------------------------------------------------------------------
; A5 ADR1 Global Serial Channel Match Address 1 80C152
; A5 OFDCON Oscillator Fail Detect Control Register 80C51GB
; A5 SETMSK Compare Register COMSET Output Mask 80C517A
; Bits in OFDCON ( not bit-adressable ):
; 0 OFDS Oscillator Fail Detect Status Flag 80C51GB
; 1
; 2
; 3
; 4
; 5
; 6
; 7
;-------------------------------------------------------------------------------
; A6 CLRMSK Compare Register COMCLR Output Mask 80C517A
; A6 WDTCON Watchdog Timer Reset Register 80C51GB
;-------------------------------------------------------------------------------
; A7 IEA Interrupt Enable A Register 80C51GB
; Bits in IEA ( not bit-adressable ):
; 0 ESEP Serial Expansion Port Interrupt Enable Bit 80C51GB
; 1 EC1 PCA1 Interrupt 6 Enable Bit 80C51GB
; 2 EX2 External Interrupt 2 Enable Bit 80C51GB
; 3 EX3 External Interrupt 3 Enable Bit 80C51GB
; 4 EX4 External Interrupt 4 Enable Bit 80C51GB
; 5 EX5 External Interrupt 5 Enable Bit 80C51GB
; 6 EWC Write Complete Interrupt Enable Bit 88F51FC
; 6 EX6 External Interrupt 6 Enable Bit 80C51GB
; 7 EAD A/D Converter Interrupt Enable Bit 80C51GB
;-------------------------------------------------------------------------------
; A8 IE Interrupt Enable Control Register 8051
; A8 IEN0 Interrupt Enable Register 0 80515
; Bits in IE/IEN0:
; Bit address Name Function Resident in
; A8 IE.0 EX0 Enable Internal Interrupt 0 8051
; A9 IE.1 ET0 Enable Timer 0 Overflow Interrupt 8051
; AA IE.2 EX1 Enable Internal Interrupt 1 8051
; AB IE.3 ET1 Enable Timer 1 Overflow Interrupt 8051
; AC IE.4 ES Enable Serial Port Interrupt 8051
; AD IE.5 ET2 Enable Timer 2 Interrupt 8052
; AE IE.6 EC Enable PCA Interrupt 80C51FX
; AE IE.6 WDT Watchdog Timer Refresh Flag 80515
; AF IE.7 EA Global Interrupt Enable/Disable 8051
; AF IE.7 EAL Enable all Interrupts 80515
;-------------------------------------------------------------------------------
; A9 IP0 Interrupt Priority Register 0 80515 80C517
; A9 SADDR Slave Address Register 80C52
; A9 SADDR0 Slave Address Register 0 80C320
; Bits in IP0 ( not bit-adressable ):
; 0 IP0_0 Priority Level Bit 0 IE0/IADC 80515 80C517
; 0 IP0_0 Priority Level Bit 0 IE0/RI1+TI1/IADC 80C517
; 1 IP0_1 Priority Level Bit 0 TF0/IEX2 80515 80C517
; 2 IP0_2 Priority Level Bit 0 IE1/IEX3 80515 80C517
; 2 IP0_2 Priority Level Bit 0 IE1/ICMP0-7/IEX3 80C517A
; 3 IP0_3 Priority Level Bit 0 TF1/IEX4 80515 80C517
; 3 IP0_3 Priority Level Bit 0 TF1/CTF/IEX4 80C517
; 4 IP0_4 Priority Level Bit 0 RI+TI/IEX5 80515 80C517
; 4 IP0_4 Priority Level Bit 0 RI+TI/ICS/IEX5 80C517A
; 5 IP0_5 Priority Level Bit 0 TF2+EXF2/IEX6 80515 80C517
; 5 IP0_5 Priority Level Bit 0 TF2+EXF2/ICR/IEX6 80C517A
; 6 WDTS Watchdog Timer Status Flag 80515
; 7 OWDS Oscillator Watchdog Timer Status Flag 80C517
;-------------------------------------------------------------------------------
; AA C1CAP0L PCA1 Compare/Capture Register 0 Low Byte 80C51GB
; AA S0RELL Baudrate 0 Timer Reload Value, Low Byte 80C517
; AA SADDR1 Slave Address Register 1 80C320
; AB C1CAP1L PCA1 Compare/Capture Register 1 Low Byte 80C51GB
; AC C1CAP2L PCA1 Compare/Capture Register 2 Low Byte 80C51GB
; AD C1CAP3L PCA1 Compare/Capture Register 3 Low Byte 80C51GB
; AE C1CAP4L PCA1 Compare/Capture Register 4 Low Byte 80C51GB
; AF CL1 PCA1 Timer/Counter Register Low Byte 80C51GB
;-------------------------------------------------------------------------------
; B0 P3 Port 3 8051
; Bits in P3:
; Bit address Name Function Resident in
; B0 P3.0 Parallel I/O Port 3 Bit 0 8051
; B0 P3.0 TXD Serial Output Port 8051
; B0 P3.0 TXD0 Serial Output Channel 0 80C517
; B1 P3.1 Parallel I/O Port 3 Bit 1 8051
; B1 P3.1 RXD Serial Input Port 8051
; B1 P3.1 RXD0 Serial Input Channel 0 80C517
; B2 P3.2 Parallel I/O Port 3 Bit 2 8051
; B2 P3.2 nINT0 External Interrupt 0 8051
; B3 P3.3 Parallel I/O Port 3 Bit 3 8051
; B3 P3.3 nINT1 External Interrupt 1 8051
; B4 P3.4 Parallel I/O Port 3 Bit 4 8051
; B4 P3.4 T0 Timer/Counter 0 External Input 8051
; B5 P3.5 Parallel I/O Port 3 Bit 5 8051
; B5 P3.5 T1 Timer/Counter 1 External Input 8051
; B6 P3.6 Parallel I/O Port 3 Bit 6 8051
; B6 P3.6 nWR External Data Memory Write Strobe 8031
; B7 P3.7 Parallel I/O Port 3 Bit 7 8051
; B7 P3.7 nRD External Data Memory Read Strobe 8031
;-------------------------------------------------------------------------------
; B1 SYSCON XRAM Control Register 80C517A
; Bits in SYSCON ( not bit-adressable ):
; 0 XMAP0 Global Disable Internal XRAM 80C517A
; 1 XMAP1 Activate nRD/nWR at Internal XRAM Access 80C517A
; 2
; 3
; 4
; 5
; 6
; 7
;-------------------------------------------------------------------------------
; B2 SARL1 DMA Source Address 1 (LOW) 80C152/452
; B3 SARH1 DMA Source Address 1 (HIGH) 80C152/452
; B4 ADRES3 A/D Conversion Result of Channel 3, ACH0-3 80C51GB
; B4 SLOTTM Global Serial Channel Slot Time 80C152
;-------------------------------------------------------------------------------
; B5 ADR2 Global Serial Channel Match Address 2 80C152
; B5 IPA1 Interrupt A Priority Register 1 80C51GB
; B5 IPAH Interrupt A Priority High Register 88F51FC
; Bits in IPA1 ( not bit-adressable ):
; 0 PSEP_1 Serial Expansion Port Priority High Bit 80C51GB
; 1 PC1_1 PCA1 Interrupt Priority High Bit 80C51GB
; 2 PX2_1 External Interrupt 2 Priority High Bit 80C51GB
; 3 PX3_1 External Interrupt 3 Priority High Bit 80C51GB
; 4 PX4_1 External Interrupt 4 Priority High Bit 80C51GB
; 5 PX5_1 External Interrupt 5 Priority High Bit 80C51GB
; 6 PX6_1 External Interrupt 6 Priority High Bit 80C51GB
; 7 PAD_1 A/D Converter Interrupt Priority High Bit 80C51GB
; Bits in IPAH ( not bit-adressable ):
; 0
; 1
; 2
; 3
; 4
; 5
; 6 PWCH Write Complete Interrupt Priority High Bit 88F51FC
; 7
;-------------------------------------------------------------------------------
; B6 IPA Interrupt A Priority Register 80C51GB
; Bits in IPA ( not bit-adressable ):
; 0 PSEP Serial Expansion Port Priority Low Bit 80C51GB
; 1 PC1 PCA1 Interrupt Priority Low Bit 80C51GB
; 2 PX2 External Interrupt 2 Priority Low Bit 80C51GB
; 3 PX3 External Interrupt 3 Priority Low Bit 80C51GB
; 4 PX4 External Interrupt 4 Priority Low Bit 80C51GB
; 5 PX5 External Interrupt 5 Priority Low Bit 80C51GB
; 6 PWC Write Complete Interrupt Priority Low Bit 88F51FC
; 6 PX6 External Interrupt 6 Priority Low Bit 80C51GB
; 7 PAD A/D Converter Interrupt Priority Low Bit 80C51GB
;-------------------------------------------------------------------------------
; B7 IP1 Interrupt Priority Register 1 80C51GB
; B7 IPH Interrupt Priority High Register 80C54/58 80C51FC
; Bits in IP1 ( not bit-adressable ):
; 0 PX0_1 External Interrupt 0 Priority High Bit 80C51GB
; 1 PT0_1 Timer 0 Interrupt Priority High Bit 80C51GB
; 2 PX1_1 External Interrupt 1 Priority High Bit 80C51GB
; 3 PT1_1 Timer 1 Interrupt Priority High Bit 80C51GB
; 4 PS_1 Serial Port Interrupt Priority High Bit 80C51GB
; 5 PT2_1 Timer 2 Interrupt Priority High Bit 80C51GB
; 6 PC_1 PCA Interrupt Priority High Bit 80C51GB
; 7
; Bits in IPH ( not bit-adressable ):
; 0 PX0H External Interrupt 0 Priority High Bit 80C54/58
; 1 PT0H Timer 0 Interrupt Priority High Bit 80C54/58
; 2 PX1H External Interrupt 1 Priority High Bit 80C54/58
; 3 PT1H Timer 1 Interrupt Priority High Bit 80C54/58
; 4 PSH Serial Port Interrupt Priority High Bit 80C54/58
; 5 PT2H Timer 2 Interrupt Priority High Bit 80C54/58
; 6 PPCH PCA Interrupt Priority High Bit 80C51FC
; 7
;-------------------------------------------------------------------------------
; B8 IEN1 Interrupt Enable Register 1 80515
; B8 IP Interrupt Priority Control 8051
; Bits in IEN1:
; Bit address Name Function Resident in
; B8 IP.0 EADC Enable A/D Converter Interrupt 80515
; B9 IP.1 EX2 Enable External Interrupt 2 80515
; BA IP.2 EX3 Enable External Interrupt 3 80515
; BB IP.3 EX4 Enable External Interrupt 4 80515
; BC IP.4 EX5 Enable External Interrupt 5 80515
; BD IP.5 EX6 Enable External Interrupt 6 80515
; BE IP.6 SWDT Watchdog Timer Start/Refresh Flag 80515
; BF IP.7 EXEN2 Enable Timer 2 External Reload Interrupt 80515
; Bits in IP:
; Bit address Name Function Resident in
; B8 IP.0 PX0 External Interrupt 0 Priority Level 8051
; B9 IP.1 PT0 Timer 0 Interrupt Priority Level 8051
; BA IP.2 PX1 External Interrupt 1 Priority Level 8051
; BB IP.3 PT1 Timer 1 Interrupt Priority Level 8051
; BC IP.4 PS Serial Port Interrupt Priority Level 8051
; BC IP.4 PS0 Serial Port 0 Interrupt Priority Level 80C320
; BD IP.5 PT2 Timer 2 Interrupt Priority Level 8052
; BE IP.6 PPC PCA Interrupt Priority Bit 80C51FX
; BE IP.6 PS1 Serial Port 1 Interrupt Priority Level 80C320
; BF IP.7
;-------------------------------------------------------------------------------
; B9 IP1 Interrupt Priority Register 1 80515 80C517
; B9 SADEN Slave Address Mask Enable Register 80C52
; B9 SADEN0 Slave Address Mask Enable Register 0 80C320
; Bits in IP1 ( not bit-adressable ):
; 0 IP1_0 Priority Level Bit 1 IE0/IADC 80515 80C517
; 0 IP1_0 Priority Level Bit 1 IE0/RI1+TI1/IADC 80C517
; 1 IP1_1 Priority Level Bit 1 TF0/IEX2 80515 80C517
; 2 IP1_2 Priority Level Bit 1 IE1/IEX3 80515 80C517
; 2 IP1_2 Priority Level Bit 1 IE1/ICMP0-7/IEX3 80C517A
; 3 IP1_3 Priority Level Bit 1 TF1/IEX4 80515 80C517
; 3 IP1_3 Priority Level Bit 1 TF1/CTF/IEX4 80C517
; 4 IP1_4 Priority Level Bit 1 RI+TI/IEX5 80515 80C517
; 4 IP1_4 Priority Level Bit 1 RI+TI/ICS/IEX5 80C517A
; 5 IP1_5 Priority Level Bit 1 TF2+EXF2/IEX6 80515 80C517
; 5 IP1_5 Priority Level Bit 1 TF2+EXF2/ICR/IEX6 80C517A
; 6
; 7
;-------------------------------------------------------------------------------
; BA C1CAP0H PCA1 Compare/Capture Register 0 High Byte 80C51GB
; BA S0RELH Baudrate 0 Timer Reload Value, High Byte 80C517
; BA SADEN1 Slave Address Mask Enable Register 1 80C320
; BB C1CAP1H PCA1 Compare/Capture Register 1 High Byte 80C51GB
; BB S1RELH Baudrate 1 Timer Reload Value, High Byte 80C517
; BC C1CAP2H PCA1 Compare/Capture Register 2 High Byte 80C51GB
; BD C1CAP3H PCA1 Compare/Capture Register 3 High Byte 80C51GB
; BE C1CAP4H PCA1 Compare/Capture Register 4 High Byte 80C51GB
; BF CH1 PCA1 Timer/Counter Register High Byte 80C51GB
;-------------------------------------------------------------------------------
; C0 IRCON Interrupt Request Control Register 80515 80C517
; C0 IRCON0 Interrupt Request Control Register 80C517A
; C0 P4 Port 4 80C51GB
; C0 P4 Port 4 DMA Source Address 80C452
; C0 SCON1 Serial Port 1 Control 80C320
; Bits in IRCON/IRCON0:
; Bit address Name Function Resident in
; C0 IRCON.0 IADC A/D Converter Interrupt Request Flag 80515
; C1 IRCON.1 IEX2 External Interrupt 2 Edge Flag 80515
; C2 IRCON.2 IEX3 External Interrupt 3 Edge Flag 80515
; C3 IRCON.3 IEX4 External Interrupt 4 Edge Flag 80515
; C4 IRCON.4 IEX5 External Interrupt 5 Edge Flag 80515
; C5 IRCON.5 IEX6 External Interrupt 6 Edge Flag 80515
; C6 IRCON.6 TF2 Timer 2 Overflow Flag 80515
; C7 IRCON.7 EXF2 Timer 2 External Reload Flag 80515
; Bits in P4:
; Bit address Name Function Resident in
; C0 P4.0 Parallel I/O Port 4 Bit 0 80C51GB
; C0 P4.0 SEPCLK Clock Source for Serial Expansion Port 80C51GB
; C1 P4.1 Parallel I/O Port 4 Bit 1 80C51GB
; C0 P4.1 SEPDAT Data I/O for Serial Expansion Port 80C51GB
; C2 P4.2 Parallel I/O Port 4 Bit 2 80C51GB
; C2 P4.2 C1 PCA1 External Clock Input 80C51GB
; C3 P4.3 Parallel I/O Port 4 Bit 3 80C51GB
; C3 P4.3 C1EX0 PCA1.0 Capture Input, Compare/PWM Output 80C51GB
; C4 P4.4 Parallel I/O Port 4 Bit 4 80C51GB
; C3 P4.4 C1EX1 PCA1.1 Capture Input, Compare/PWM Output 80C51GB
; C5 P4.5 Parallel I/O Port 4 Bit 5 80C51GB
; C3 P4.5 C1EX2 PCA1.2 Capture Input, Compare/PWM Output 80C51GB
; C6 P4.6 Parallel I/O Port 4 Bit 6 80C51GB
; C3 P4.6 C1EX3 PCA1.3 Capture Input, Compare/PWM Output 80C51GB
; C7 P4.7 Parallel I/O Port 4 Bit 7 80C51GB
; C7 P4.7 C1EX4 PCA1.4 Capture Input, Compare/PWM Output 80C51GB
; Bits in SCON1:
; Bit address Name Function Resident in
; C0 SCON1.0 RI_1 Receiver Interrupt Flag 80C320
; C1 SCON1.1 TI_1 Transmitter Interrupt Flag 80C320
; C2 SCON1.2 RB8_1 9th Received Bit State 80C320
; C3 SCON1.3 TB8_1 9th Transmission Bit State 80C320
; C4 SCON1.4 REN_1 Receive Enable 80C320
; C5 SCON1.5 SM2_1 Multiple CPU Communucations/Mode Bit 2 80C320
; C6 SCON1.6 SM1_1 Serial Port 1 Mode Bit 1 80C320
; C7 SCON1.7 SM0_1 Serial Port 1 Mode Bit 0 (SMOD0=0) 80C320
; C7 SCON1.7 FE_1 Framing Error Flag (SMOD0=1) 80C320
;-------------------------------------------------------------------------------
; C1 CCEN Compare/Capture Enable Register 80515
; C1 SBUF1 Serial Data Buffer 1 80C320
; Bits in CCEN ( not bit-adressable ):
; 0 COCAL0 Compare/Capture Mode for CRCL/H Bit 0 80515
; 1 COCAH0 Compare/Capture Mode for CRCL/H Bit 1 80515
; 2 COCAL1 Compare/Capture Mode for CCL/H1 Bit 0 80515
; 3 COCAH1 Compare/Capture Mode for CCL/H1 Bit 1 80515
; 4 COCAL2 Compare/Capture Mode for CCL/H2 Bit 0 80515
; 5 COCAH2 Compare/Capture Mode for CCL/H2 Bit 1 80515
; 6 COCAL3 Compare/Capture Mode for CCL/H3 Bit 0 80515
; 7 COCAH3 Compare/Capture Mode for CCL/H3 Bit 1 80515
;-------------------------------------------------------------------------------
; C2 CCL1 Compare/Capture Register 1, Low Byte 80515
; C2 DARL0 DMA Destination Address 0 (LOW) 80C152/452
; C2 ROMSIZE ROM Size Select 87C520
; Bits in ROMSIZE ( not bit-adressable ):
; 0 RS0 ROM Size Select Bit 0 87C520
; 1 RS1 ROM Size Select Bit 1 87C520
; 2 RS2 ROM Size Select Bit 2 87C520
; 3
; 4
; 5
; 6
; 7
;-------------------------------------------------------------------------------
; C3 CCH1 Compare/Capture Register 1, High Byte 80515
; C3 DARH0 DMA Destination Address 0 (HIGH) 80C152/452
;-------------------------------------------------------------------------------
; C4 ADRES4 A/D Conversion Result of Channel 4, ACH4 80C51GB
; C4 BKOFF Global Serial Channel Backoff Timer 80C152
; C4 CCL2 Compare/Capture Register 2, Low Byte 80515
; C4 PMR Power Management Register 87C520
; Bits in PMR ( not bit-adressable ):
; 0 DME0 Data Memory Enable Bit 0 87C520
; 1 DME1 Data Memory Enable Bit 1 87C520
; 2 ALEOFF ALE Disable 87C520
; 3 XTOFF Crystal Oscillator Disable 87C520
; 4 reserved 87C520
; 5 SWB Switchback Enable 87C520
; 6 CD0 Clock Divide Control Bit 0 87C520
; 7 CD1 Clock Divide Control Bit 1 87C520
;-------------------------------------------------------------------------------
; C5 ADR3 Global Serial Channel Match Address 3 80C152
; C5 CCH2 Compare/Capture Register 2, High Byte 80515
; C5 STATUS Status Register 80C310
; Bits in STATUS ( not bit-adressable ):
; 0 SPRA0 Serial Port 0 Receive Activity Monitor 87C520
; 1 SPTA0 Serial Port 0 Transmit Activity Monitor 87C520
; 2 SPRA1 Serial Port 0 Receive Activity Monitor 87C520
; 3 SPTA1 Serial Port 1 Transmit Activity Monitor 87C520
; 4 XTUP Crystal Oscillator Warm-Up Status 87C520
; 5 LIP Low Priority Interrupt Status 80C310
; 6 HIP High Priority Interrupt Status 80C310
; 7 PIP Power Fail Priority Interrupt Status 80C320
;-------------------------------------------------------------------------------
; C6 CCL3 Compare/Capture Register 3, Low Byte 80515
; C6 EXICON External Interrupt Control Register 80C51GB
; Bits in EXICON ( not bit-adressable ):
; 0 IT2 Interrupt 2 Transition Control Bit 80C51GB
; 1 IT3 Interrupt 3 Transition Control Bit 80C51GB
; 2 IE2 Interrupt 2 Edge Flag 80C51GB
; 3 IE3 Interrupt 3 Edge Flag 80C51GB
; 4 IE4 Interrupt 4 Edge Flag 80C51GB
; 5 IE5 Interrupt 5 Edge Flag 80C51GB
; 6 IE6 Interrupt 6 Edge Flag 80C51GB
; 7
;-------------------------------------------------------------------------------
; C7 ACMP A/D Compare Register 80C51GB
; C7 CCH3 Compare/Capture Register 3, High Byte 80515
; C7 TA Timed Access Register 80C320
; Bits in ACMP ( not bit-adressable ):
; 0 CMP7 A/D Comparison Result ACH7 with COMPREF 80C51GB
; 1 CMP6 A/D Comparison Result ACH6 with COMPREF 80C51GB
; 2 CMP5 A/D Comparison Result ACH5 with COMPREF 80C51GB
; 3 CMP4 A/D Comparison Result ACH4 with COMPREF 80C51GB
; 4 CMP3 A/D Comparison Result ACH3 with COMPREF 80C51GB
; 5 CMP2 A/D Comparison Result ACH2 with COMPREF 80C51GB
; 6 CMP1 A/D Comparison Result ACH1 with COMPREF 80C51GB
; 7 CMP0 A/D Comparison Result ACH0 with COMPREF 80C51GB
;-------------------------------------------------------------------------------
; C8 IEN1 Interrupt Enable Register 1 80C152
; C8 T2CON Timer/Counter 2 Control Register 8052 80515
; C8 STS Status/Command Register 8044
; Bits in IEN1:
; Bit address Name Function Resident in
; C8 IEN1.0 EGSRV Enable GSC Receive Valid Interrupt 80C152
; C9 IEN1.1 EGSRE Enable GSC Receive Error Interrupt 80C152
; CA IEN1.2 EDMA0 Enable DMA Channel 0 Done Interrupt 80C152
; CB IEN1.0 EGSTV Enable GSC Transmit Valid Interrupt 80C152
; CC IEN1.4 EDMA1 Enable DMA Channel 1 Done Interrupt 80C152
; CD IEN1.5 EGSTE Enable GSC Transmit Error Interrupt 80C152
; CE IEN1.6
; CF IEN1.7
; Bits in STS:
; Bit address Name Function Resident in
; C8 STS.0 RBP Receive Buffer Protect 8044
; C9 STS.1 AM Auto Mode/Addressed Mode 8044
; CA STS.2 OPB Optional Poll Bit 8044
; CB STS.3 BOV Receive Buffer Overrun 8044
; CC STS.4 SI SIU Interrupt 8044
; CD STS.5 RTS Request to Send 8044
; CE STS.6 RBE Receive Buffer Empty 8044
; CF STS.7 TBF Transmit Buffer Full 8044
; Bits in T2CON:
; Bit address Name Function Resident in
; C8 T2CON.0 CP_RL2 Capture/Reload Select Timer 2 8052
; C8 T2CON.0 T2I0 Timer 2 Input Selection Bit 0 80515
; C9 T2CON.1 C_T2 Timer or Counter Select Timer 2 8052
; C9 T2CON.1 T2I1 Timer 2 Input Selection Bit 1 80515
; CA T2CON.2 T2R0 Timer 2 Reload Mode Selection Bit 0 80515
; CA T2CON.2 TR2 Timer 2 Run Start/Stop Control 8052
; CB T2CON.3 EXEN2 Timer 2 External Enable 8052
; CB T2CON.3 T2R1 Timer 2 Reload Mode Selection Bit 1 80515
; CC T2CON.4 T2CM Timer 2 Compare Mode Bit for CRC, CC1-CC3 80515
; CC T2CON.4 TCLK Transmit Clock Enable 8052
; CD T2CON.5 I2FR External Interrupt 2 Rising Edge Flag 80515
; CD T2CON.5 RCLK Receive Clock Enable 8052
; CE T2CON.6 EXF2 Timer 2 External Flag 8052
; CE T2CON.6 I3FR External Interrupt 3 Rising Edge Flag 80515
; CF T2CON.7 T2PS Timer 2 Prescaler Select Bit 80515
; CF T2CON.7 T2PS0 Timer 2 Prescaler Select Bit 0 80C517
; CF T2CON.7 TF2 Timer 2 Overflow Flag 8052
;-------------------------------------------------------------------------------
; C9 CC4EN Compare/Capture 4 Enable Register 80C517
; C9 SMD Serial Mode Register 8044
; C9 T2MOD Timer 2 Mode Control Register 80C52
; Bits in CC4EN ( not bit-adressable ):
; 0 COMO Compare Mode Bit 80C517
; 1 COCAL4 Compare/Capture Mode for CC4 Register Bit 0 80C517
; 2 COCAH4 Compare/Capture Mode for CC4 Register Bit 1 80C517
; 3 COCOEN Enable Concurrent Compare Output for CC4 80C517
; 3 COCOEN0 Enable Concurrent Compare Mode Bit 0 80C517A
; 4 COCON0 Select Concurrent Compare Output Bit 0 80C517
; 5 COCON1 Select Concurrent Compare Output Bit 1 80C517
; 6 COCON2 Select Concurrent Compare Output Bit 2 80C517
; 7 COCOEN1 Enable Concurrent Compare Mode Bit 1 80C517A
; Bits in SMD ( not bit-adressable ):
; 0 NFCS No FCS Field in the SDLC Frame 8044
; 1 NB Non-Buffered Mode, No Control Field 8044
; 2 PFS Pre-Frame Sync Mode 8044
; 3 LOOP Loop Configuration 8044
; 4 NRZI NRZI Coding Option 8044
; 5 SCM0 Select Clock Mode Bit 0 8044
; 6 SCM1 Select Clock Mode Bit 1 8044
; 7 SCM2 Select Clock Mode Bit 2 8044
; Bits in T2MOD ( not bit-adressable ):
; 0 DCEN Timer 2 Down Counter Enable 80C52
; 1 T2OE Timer 2 Output Enable Bit 87C51FC
; 2
; 3
; 4
; 5
; 6
; 7
;-------------------------------------------------------------------------------
; CA CRCL Compare/Reload/Capture Register, Low Byte 80515
; CA RCAP2L T/C 2 Capture Register Low Byte 8052
; CA RCB Receive Control Byte Register 8044
; CB CRCH Compare/Reload/Capture Register, High Byte 80515
; CB RBL Receive Buffer Length Register 8044
; CB RCAP2H T/C 2 Capture Register High Byte 8052
; CC RBS Receive Buffer Start Address Register 8044
; CC TL2 Timer/Counter Low Byte 8052
; CD RFL Receive Field Length Register 8044
; CD TH2 Timer/Counter High Byte 8052
;-------------------------------------------------------------------------------
; CE CCL4 Compare/Capture Register 4, Low Byte 80C517
; CE FCON Flash Control Register 88F51FC
; CE STAD Station Address Register 8044
; Bits in FCON ( not bit-adressable ):
; 0 PGMnERS Programm/notErase Bit 88F51FC
; 1 WRnVER Write/notVerify Bit 88F51FC
; 2 HV High Voltage Bit 88F51FC
; 3 AR Address Range Bit 88F51FC
; 4 AS Address Space Bit 88F51FC
; 5 CNFG Flash Configuration Bit 88F51FC
; 6 WC Write Complete Bit 88F51FC
; 7 WIE Write Interrupt Enable Bit 88F51FC
;-------------------------------------------------------------------------------
; CF CCH4 Compare/Capture Register 4, High Byte 80C517
; CF DMACNT DMA Count Register 8044
; CF FT Flash Timing Register 88F51FC
; Bits in FT ( not bit-adressable ):
; 0 FT0 Programm/Erase Pulse Duration Bit 0 88F51FC
; 1 FT1 Programm/Erase Pulse Duration Bit 1 88F51FC
; 2 FT2 Programm/Erase Pulse Duration Bit 2 88F51FC
; 3 FT3 Programm/Erase Pulse Duration Bit 3 88F51FC
; 4 S0 Programm/Erase Pulse Duartion Bit 4 88F51FC
; 5 S1 Programm/Erase Pulse Duartion Bit 5 88F51FC
; 6 SWPP Swap Preparation Bit 88F51FC
; 7
;-------------------------------------------------------------------------------
; D0 PSW Program Status Word 8051
; Bits in PSW:
; Bit address Name Function Resident in
; D0 PSW.0 P Parity Flag 8051
; D1 PSW.1 F1 User Definable Flag 8051
; D2 PSW.2 OV Overflow Flag 8051
; D3 PSW.3 RS0 Register Bank Selector Bit 0 8051
; D4 PSW.4 RS1 Register Bank Selector Bit 1 8051
; D5 PSW.5 F0 Flag 0, General Purpose Flag 8051
; D6 PSW.6 AC Auxiliary Carry Flag 8051
; D7 PSW.7 CY Carry Flag 8051
;-------------------------------------------------------------------------------
; D1 IRCON1 Interrupt Control Register 1 80C517A
; Bits in IRCON1 ( not bit-adressable ):
; 0 ICMP0 Compare 0 Interrupt Request Flag 80C517A
; 1 ICMP1 Compare 1 Interrupt Request Flag 80C517A
; 2 ICMP2 Compare 2 Interrupt Request Flag 80C517A
; 3 ICMP3 Compare 3 Interrupt Request Flag 80C517A
; 4 ICMP4 Compare 4 Interrupt Request Flag 80C517A
; 5 ICMP5 Compare 5 Interrupt Request Flag 80C517A
; 6 ICMP6 Compare 6 Interrupt Request Flag 80C517A
; 7 ICMP7 Compare 7 Interrupt Request Flag 80C517A
;-------------------------------------------------------------------------------
; D2 CML0 Compare Register 0, Low Byte 80C517
; D2 DARL1 DMA Destination Address 1 (LOW) 80C152/452
; D3 CMH0 Compare Register 0, High Byte 80C517
; D3 DARH1 DMA Destination Address 1 (HIGH) 80C152/452
; D4 ADRES5 A/D Conversion Result of Channel 5, ACH5 80C51GB
; D4 CML2 Compare Register 2, Low Byte 80C517
; D4 TCDCNT GSC Transmit Collision Counter 80C152
; D5 CMH1 Compare Register 1, High Byte 80C517
; D5 AMSK0 Global Serial Channel Address Mask 0 80C152
; D6 CML2 Compare Register 2, Low Byte 80C517
;-------------------------------------------------------------------------------
; D7 CMH2 Compare Register 2, High Byte 80C517
; D7 SEPCON Serial Expansion Port Control Register 80C51GB
; Bits in SEPCON ( not bit-adressable ):
; 0 SEPS0 Serial Expansion Port Speed Select Bit 0 80C51GB
; 1 SEPS1 Serial Expansion Port Speed Select Bit 1 80C51GB
; 2 CLKPH Clock Phase for Data Sample on SEPCLK Edge 80C51GB
; 3 CLKP Clock Polarity 80C51GB
; 4 SEPREN Serial Expansion Port Receive Enable 80C51GB
; 5 SEPE Serial Expansion Port Enable 80C51GB
; 6
; 7
;-------------------------------------------------------------------------------
; D8 ADCON A/D Converter Control Register 80515
; D8 ADCON0 A/D Converter Control Register 0 80C517
; D8 CCON PCA Counter Control Register 80C51FX
; D8 NSNR Send/Receive Count Register 8044
; D8 TSTAT Transmit Status ( DMA and GSC ) 80C152
; D8 WDCON Serial Port 0 Receive Activity Monitor 80C310
; Bits in ADCON/ADCON0:
; Bit address Name Function Resident in
; D8 ADCON.0 MX0 A/D Input Channel Multiplex Address Bit 0 80515
; D9 ADCON.1 MX1 A/D Input Channel Multiplex Address Bit 1 80515
; DA ADCON.2 MX2 A/D Input Channel Multiplex Address Bit 2 80515
; DB ADCON.3 ADM A/D Conversion Mode Continuous 80515
; DC ADCON.4 BSY Busy Flag, Conversion in Progress 80515
; DD ADCON.5 ADEX External Start of A/D Conversion 80C517
; DE ADCON.6 CLK Clock Out Enable Bit 80515
; DF ADCON.7 BD Baud Rate Enable 80515
; Bits in CCON:
; Bit address Name Function Resident in
; D8 CCON.0 CCF0 PCA Module 0 Interrupt Flag 80C51FX
; D9 CCON.1 CCF1 PCA Module 1 Interrupt Flag 80C51FX
; DA CCON.2 CCF2 PCA Module 2 Interrupt Flag 80C51FX
; DB CCON.3 CCF3 PCA Module 3 Interrupt Flag 80C51FX
; DC CCON.4 CCF4 PCA Module 4 Interrupt Flag 80C51FX
; DD CCON.5
; DE CCON.6 CR PCA Counter Run Control Bit 80C51FX
; DF CCON.7 CF PCA Counter Overflow Flag 80C51FX
; Bits in NSNR:
; Bit address Name Function Resident in
; D8 NSNR.0 SER Receive Sequence Error 8044
; D9 NSNR.1 NR0 Receive Sequence Counter Bit 0 8044
; DA NSNR.2 NR1 Receive Sequence Counter Bit 1 8044
; DB NSNR.3 NR2 Receive Sequence Counter Bit 2 8044
; DC NSNR.4 SES Send Sequence Error 8044
; DD NSNR.5 NS0 Send Sequence Counter Bit 0 8044
; DE NSNR.6 NS1 Send Sequence Counter Bit 1 8044
; DF NSNR.7 NS2 Send Sequence Counter Bit 2 8044
; Bits in TSTAT:
; Bit address Name Function Resident in
; D8 TSTAT.0 DMA DMA Select 80C152
; D9 TSTAT.1 TEN Transmit Enable 80C152
; DA TSTAT.2 TFNF Transmit FIFO Not Full 80C152
; DB TSTAT.3 TDN Transmit Done 80C152
; DC TSTAT.4 TCDT Transmit Collision Detect 80C152
; DD TSTAT.5 UR Underrun 80C152
; DE TSTAT.6 NOACK No Acknowledge 80C152
; DF TSTAT.7 LNI Line Idle 80C152
; Bits in WDCON:
; Bit address Name Function Resident in
; D8 WDCON.0 RWT Reset Watchdog Timer 80C320
; D9 WDCON.1 EWT Enable Watchdog Timer Reset 80C320
; DA WDCON.2 WTRF Watchdog Timer Reset Flag 80C320
; DB WDCON.3 WTIF Watchdog Interrupt Flag 80C320
; DC WDCON.4 PFI Power-Fail Interrupt Flag 80C320
; DD WDCON.5 EPFI Enable Power-Fail Interrupt 80C320
; DE WDCON.6 POR Power-On Reset Flag 80C310
; DF WDCON.7 SMOD_1 Serial Port 1 Baudrate Doubling Modificator 80C320
;-------------------------------------------------------------------------------
; D9 ADDAT A/D Converter Data Register 80515 80C517
; D9 ADDATH A/D Converter Data Register, High Byte 80C517A
; D9 CMOD PCA Counter Mode Register 80C51FX
; D9 SIUST SIU State Counter 8044
; Bits in CMOD ( not bit-adressable ):
; 0 ECF PCA Enable Counter Overflow Interrupt 80C51FX
; 1 CPS0 PCA Count Pulse Select Bit 0 80C51FX
; 2 CPS1 PCA Count Pulse Select Bit 1 80C51FX
; 3
; 4
; 5
; 6 WDTE Watchdog Timer Enable 80C51FX
; 7 CIDL Counter Idle Control 80C51FX
;-------------------------------------------------------------------------------
; DA ADDATL A/D Converter Data Register, Low Byte 80C517A
; DA CCAPM0 PCA Module Compare/Capture Register 0 80C51FX
; DA DAPR D/A Converter Program Register 80515 80C517
; DA TCB Transmit Control Byte Register 8044
; Bits in CCAPM0 ( not bit-adressable ):
; 0 ECCF0 Enable Compare/Capture Flag 0 Interrupt 80C51FX
; 1 PWM0 Pulse Width Modulation Mode on CEX0 80C51FX
; 2 TOG0 Toggle on CEX0 80C51FX
; 3 MAT0 Match Compare/Capture Register 0 80C51FX
; 4 CAPN0 Capture Negative Edge on CEX0 80C51FX
; 5 CAPP0 Capture Positive Edge on CEX0 80C51FX
; 6 ECOM0 Enable Comparator Register 0 80C51FX
; 7
; Bits in DAPR ( not bit-adressable ):
; 0 VAGND0 Programming of VIntAGND Bit 0 80515
; 1 VAGND1 Programming of VIntAGND Bit 1 80515
; 2 VAGND2 Programming of VIntAGND Bit 2 80515
; 3 VAGND3 Programming of VIntAGND Bit 3 80515
; 4 VAREF0 Programming of VIntAREF Bit 0 80515
; 5 VAREF1 Programming of VIntAREF Bit 1 80515
; 6 VAREF2 Programming of VIntAREF Bit 2 80515
; 7 VAREF3 Programming of VIntAREF Bit 3 80515
;-------------------------------------------------------------------------------
; DB CCAPM1 PCA Module Compare/Capture Register 1 80C51FX
; DB P6 Port 6 ( Inputs Only ) 80C515
; DB P7 Port 7 ( Inputs Only ) 80C517
; DB TBL Transmit Buffer Length Register 8044
; Bits in CCAPM1 ( not bit-adressable ):
; 0 ECCF1 Enable Compare/Capture Flag 1 Interrupt 80C51FX
; 1 PWM1 Pulse Width Modulation Mode on CEX1 80C51FX
; 2 TOG1 Toggle on CEX1 80C51FX
; 3 MAT1 Match Compare/Capture Register 1 80C51FX
; 4 CAPN1 Capture Negative Edge on CEX1 80C51FX
; 5 CAPP1 Capture Positive Edge on CEX1 80C51FX
; 6 ECOM1 Enable Comparator Register 1 80C51FX
; 7
; Bits in P6 ( not bit-adressable ):
; 0 Parallel Input Port 6 Bit 0 80C515
; 0 AIN0 Analog Input 0 80C515
; 1 Parallel Input Port 6 Bit 1 80C515
; 1 AIN1 Analog Input 1 80C515
; 2 Parallel Input Port 6 Bit 2 80C515
; 2 AIN2 Analog Input 2 80C515
; 3 Parallel Input Port 6 Bit 3 80C515
; 3 AIN3 Analog Input 3 80C515
; 4 Parallel Input Port 6 Bit 4 80C515
; 4 AIN4 Analog Input 4 80C515
; 5 Parallel Input Port 6 Bit 5 80C515
; 5 AIN5 Analog Input 5 80C515
; 6 Parallel Input Port 6 Bit 6 80C515
; 6 AIN6 Analog Input 6 80C515
; 7 Parallel Input Port 6 Bit 7 80C515
; 7 AIN7 Analog Input 7 80C515
; Bits in P7 ( not bit-adressable ):
; 0 Parallel Input Port 7 Bit 0 80C517
; 0 AIN0 Analog Input 0 80C517
; 1 Parallel Input Port 7 Bit 1 80C517
; 1 AIN1 Analog Input 1 80C517
; 2 Parallel Input Port 7 Bit 2 80C517
; 2 AIN2 Analog Input 2 80C517
; 3 Parallel Input Port 7 Bit 3 80C517
; 3 AIN3 Analog Input 3 80C517
; 4 Parallel Input Port 7 Bit 4 80C517
; 4 AIN4 Analog Input 4 80C517
; 5 Parallel Input Port 7 Bit 5 80C517
; 5 AIN5 Analog Input 5 80C517
; 6 Parallel Input Port 7 Bit 6 80C517
; 6 AIN6 Analog Input 6 80C517
; 7 Parallel Input Port 7 Bit 7 80C517
; 7 AIN7 Analog Input 7 80C517
;-------------------------------------------------------------------------------
; DC ADCON1 A/D Converter Control Register 1 80C517
; DC CCAPM2 PCA Module Compare/Capture Register 2 80C51FX
; DC TBS Transmit Buffer Start Address Register 8044
; Bits in ADCON1:
; 0 MX0 A/D Input Channel Multiplex Address Bit 0 80C517
; 1 MX1 A/D Input Channel Multiplex Address Bit 1 80C517
; 2 MX2 A/D Input Channel Multiplex Address Bit 2 80C517
; 3 MX3 A/D Input Channel Multiplex Address Bit 3 80C517
; 4
; 5
; 6
; 7 ADCL A/D Converter Clock = f.osc/16 80C517A
; Bits in CCAPM2 ( not bit-adressable ):
; 0 ECCF2 Enable Compare/Capture Flag 2 Interrupt 80C51FX
; 1 PWM2 Pulse Width Modulation Mode on CEX2 80C51FX
; 2 TOG2 Toggle on CEX2 80C51FX
; 3 MAT2 Match Compare/Capture Register 2 80C51FX
; 4 CAPN2 Capture Negative Edge on CEX2 80C51FX
; 5 CAPP2 Capture Positive Edge on CEX2 80C51FX
; 6 ECOM2 Enable Comparator Register 2 80C51FX
; 7
;-------------------------------------------------------------------------------
; DD CCAPM3 PCA Module Compare/Capture Register 3 80C51FX
; DD FIFO0 FIFO Byte 0 8044
; DD P8 Port 8 ( 4-Bit Input Port ) 80C517
; Bits in CCAPM3 ( not bit-adressable ):
; 0 ECCF3 Enable Compare/Capture Flag 3 Interrupt 80C51FX
; 1 PWM3 Pulse Width Modulation Mode on CEX3 80C51FX
; 2 TOG3 Toggle on CEX3 80C51FX
; 3 MAT3 Match Compare/Capture Register 3 80C51FX
; 4 CAPN3 Capture Negative Edge on CEX3 80C51FX
; 5 CAPP3 Capture Positive Edge on CEX3 80C51FX
; 6 ECOM3 Enable Comparator Register 3 80C51FX
; 7
; Bits in P8 ( not bit-adressable ):
; 0 Parallel Input Port 8 Bit 0 80C517
; 0 AIN8 Analog Input 8 80C517
; 1 Parallel Input Port 8 Bit 1 80C517
; 1 AIN9 Analog Input 9 80C517
; 2 Parallel Input Port 8 Bit 2 80C517
; 2 AIN10 Analog Input 10 80C517
; 3 Parallel Input Port 8 Bit 3 80C517
; 3 AIN11 Analog Input 11 80C517
; 4
; 5
; 6
; 7
;-------------------------------------------------------------------------------
; DE CCAPM4 PCA Module Compare/Capture Register 4 80C51FX
; DE CTRELL Compare Timer Reload Register, Low Byte 80C517
; DE FIFO1 FIFO Byte 1 8044
; Bits in CCAPM4 ( not bit-adressable ):
; 0 ECCF4 Enable Compare/Capture Flag 4 Interrupt 80C51FX
; 1 PWM4 Pulse Width Modulation Mode on CEX4 80C51FX
; 2 TOG4 Toggle on CEX4 80C51FX
; 3 MAT4 Match Compare/Capture Register 4 80C51FX
; 4 CAPN4 Capture Negative Edge on CEX4 80C51FX
; 5 CAPP4 Capture Positive Edge on CEX4 80C51FX
; 6 ECOM4 Enable Comparator Register 4 80C51FX
; 7
;-------------------------------------------------------------------------------
; DF CTRELH Compare Timer Reload Register, High Byte 80C517
; DF FIFO2 FIFO Byte 2 8044
;-------------------------------------------------------------------------------
; E0 ACC Accumulator 8051
; Bits in ACC:
; Bit address Name Function Resident in
; E0 ACC.0 Accumulator Data Bit 0 8051
; E1 ACC.1 Accumulator Data Bit 1 8051
; E2 ACC.2 Accumulator Data Bit 2 8051
; E3 ACC.3 Accumulator Data Bit 3 8051
; E4 ACC.4 Accumulator Data Bit 4 8051
; E5 ACC.5 Accumulator Data Bit 5 8051
; E6 ACC.6 Accumulator Data Bit 6 8051
; E7 ACC.7 Accumulator Data Bit 7 8051
;-------------------------------------------------------------------------------
; E1 CTCON Compare Timer Control Register 80C517
; Bits in CTCON ( not bit-adressable ):
; 0 CLK0 Compare Timer Input Clock Selection Bit 0 80C517
; 1 CLK1 Compare Timer Input Clock Selection Bit 1 80C517
; 2 CLK2 Compare Timer Input Clock Selection Bit 2 80C517
; 3 CTF Compare Timer Overflow Flag 80C517
; 4 ISC Interrupt Request Flag for COMSET 80C517A
; 4 ISR Interrupt Request Flag for COMCLR 80C517A
; 6
; 7 T2PS1 Timer 2 Prescaler Select Bit 1 80C517
;-------------------------------------------------------------------------------
; E2 BCRL0 DMA Byte Count 0 (LOW) 80C152/452
; E2 CML3 Compare Register 3, Low Byte 80C517
; E3 BCRH0 DMA Byte Count 0 (HIGH) 80C152/452
; E3 CMH3 Compare Register 3, High Byte 80C517
; E4 ADRES6 A/D Conversion Result of Channel 6, ACH6 80C51GB
; E4 CML4 Compare Register 4, Low Byte 80C517
; E4 PRBS GSC Pseudo-Random Binary Sequence 80C152
; E5 AMSK1 Global Serial Channel Address Mask 1 80C152
; E5 CMH4 Compare Register 4, High Byte 80C517
;-------------------------------------------------------------------------------
; E6 CML5 Compare Register 5, Low Byte 80C517
; E6 HSTAT Host Status Register 80C452
; Bits in HSTAT ( not bit-adressable ):
; 0 HST0 Input FIFO Request Service Status 80C452
; 1 HST1 FIFO DMA Freeze Mode Status 80C452
; 2 HST2 Immediate Command In SFR Status 80C452
; 3 HST3 Input FIFO Overrun Error Condition Flag 80C452
; 4 HST4 Output FIFO Request for Service Status 80C452
; 5 HST5 Data Stream Command/Data at Output FIFO 80C452
; 6 HST6 Immediate Command Out Register Status 80C452
; 7 HST7 Output FIFO Underrun Error Condition 80C452
;---------------------------------------------------------------------------
; E7 CMH5 Compare Register 5, High Byte 80C517
; E7 HCON Host Control Register 80C452
; E7 SEPDAT Serial Expansion Port Data Register 80C51GB
; Bits in HCON ( not bit-adressable ):
; 0 HC0 reserved 80C452
; 1 HC1 Select Between INTRQ and INTRQIN/INTRQOUT 80C452
; 2 HC2 reserved 80C452
; 3 HC3 Software Reset 80C452
; 4 HC4 Enable the Interrupt due to ICI Register 80C452
; 5 HC5 Enable the Interrupt due to ICO Present 80C452
; 6 HC6 Enable Input FIFO Interrupt 80C452
; 7 HC7 Enable Output FIFO Interrupt 80C452
;-------------------------------------------------------------------------------
; E8 C1CON PCA1 Counter Control Register 80C51GB
; E8 EIE Extended Interrupt Enable 80C310
; E8 P4 Port 4 ( Bidirectional ) 80515 80C517
; E8 RSTAT Receive Status ( DMA and GSC ) 80C152
; E8 SLCON Slave Control Register 80C452
; Bits in EIE:
; Bit address Name Function Resident in
; E8 EIE.0 EX2 External Interrupt 2 Enable 80C310
; E9 EIE.1 EX3 External Interrupt 3 Enable 80C310
; EA EIE.2 EX4 External Interrupt 4 Enable 80C310
; EB EIE.3 EX5 External Interrupt 5 Enable 80C310
; EC EIE.4 EWDI Watchdog Interrupt Enable 80C320
; ED EIE.5 ERTCI Real-Time Clock Interrupt Enable 87C530
; EE EIE.6
; EF EIE.7
; Bits in C1CON:
; Bit address Name Function Resident in
; E8 C1CON.0 C1CF0 PCA1 Module 0 Interrupt Flag 80C51GB
; E9 C1CON.1 C1CF1 PCA1 Module 1 Interrupt Flag 80C51GB
; EA C1CON.2 C1CF2 PCA1 Module 2 Interrupt Flag 80C51GB
; EB C1CON.3 C1CF3 PCA1 Module 3 Interrupt Flag 80C51GB
; EC C1CON.4 C1CF4 PCA1 Module 4 Interrupt Flag 80C51GB
; ED C1CON.5 CRE CR Enable Bit 80C51GB
; EE C1CON.6 CR1 PCA1 Counter Run Control Bit 80C51GB
; EF C1CON.7 CF1 PCA1 Counter Overflow Flag 80C51GB
; Bits in P4:
; Bit address Name Function Resident in
; E8 P4.0 Parallel I/O Port 4 Bit 0 80515
; E8 P4.0 CM0 Compare 0 of Compare Unit CM0-7 80C517
; E9 P4.1 Parallel I/O Port 4 Bit 1 80515
; E9 P4.1 CM1 Compare 1 of Compare Unit CM0-7 80C517
; EA P4.2 Parallel I/O Port 4 Bit 2 80515
; EA P4.2 CM2 Compare 2 of Compare Unit CM0-7 80C517
; EB P4.3 Parallel I/O Port 4 Bit 3 80515
; EB P4.3 CM3 Compare 3 of Compare Unit CM0-7 80C517
; EC P4.4 Parallel I/O Port 4 Bit 4 80515
; EC P4.4 CM4 Compare 4 of Compare Unit CM0-7 80C517
; ED P4.5 Parallel I/O Port 4 Bit 5 80515
; ED P4.5 CM5 Compare 5 of Compare Unit CM0-7 80C517
; EE P4.6 Parallel I/O Port 4 Bit 6 80515
; EE P4.6 CM6 Compare 6 of Compare Unit CM0-7 80C517
; EF P4.7 Parallel I/O Port 4 Bit 7 80515
; EF P4.7 CM7 Compare 7 of Compare Unit CM0-7 80C517
; Bits in RSTAT:
; Bit address Name Function Resident in
; E8 RSTAT.0 HABEN Hardware Based Acknowledge Enable 80C152
; E9 RSTAT.1 GREN GSC Receiver Enable 80C152
; EA RSTAT.2 RFNE Receive FIFO Not Empty 80C152
; EB RSTAT.3 RDN Receive Done 80C152
; EC RSTAT.4 CRCE CRC Error 80C152
; ED RSTAT.5 AE Alignment Error 80C152
; EE RSTAT.6 RCABT Receiver Collision/Abort Detect 80C152
; EF RSTAT.7 OVR Overrun 80C152
; Bits in SLCON:
; Bit address Name Function Resident in
; E8 SLCON.0 OFRS Output FIFO Channel Request for Service 80C452
; E9 SLCON.1 IFRS Input FIFO Channel Request for Service 80C452
; EA SLCON.2 SC2 reserved 80C452
; EB SLCON.3 FRZ Enable FIFO DMA Freeze Mode 80C452
; EC SLCON.4 ICOI Interrupt on ICO Register Available 80C452
; ED SLCON.5 ICII Interrupt on ICI Register Command Written 80C452
; EE SLCON.6 OFI Enable Output FIFO Interrupt 80C452
; EF SLCON.7 IFI Enable Input FIFO Interrupt 80C452
;-------------------------------------------------------------------------------
; E9 CL PCA Timer/Counter Register Low Byte 80C51FX
; E9 MD0 Multiplication/Division Register 0 80C517
; E9 SSTAT Slave Status Register 80C452
; Bits in SSTAT ( not bit-adressable ):
; 0 SST0 Input FIFO Request for Service Flag 80C452
; 1 SST1 Data Stream Command/Data at Input FIFO Flag 80C452
; 2 SST2 Immediate Command In SFR Status 80C452
; 3 SST3 Input FIFO Underrun Error Condition Flag 80C452
; 4 SST4 Output FIFO Request for Service Flag 80C452
; 5 SST5 FIFO DMA Freeze Mode Status 80C452
; 6 SST6 Immediate Command Out Register Status 80C452
; 7 SST7 Output FIFO Overrun Error Condition Flag 80C452
;-------------------------------------------------------------------------------
; EA CCAP0L PCA Compare/Capture Register 0 Low Byte 80C51FX
; EA IWPR Input Write Pointer 80C452
; EA MD1 Multiplication/Division Register 1 80C517
; EB CCAP1L PCA Compare/Capture Register 1 Low Byte 80C51FX
; EB IRPR Input Read Pointer 80C452
; EB MD2 Multiplication/Division Register 2 80C517
; EC CBP Channel Boundary Pointer 80C452
; EC CCAP2L PCA Compare/Capture Register 2 Low Byte 80C51FX
; EC MD3 Multiplication/Division Register 3 80C517
; ED CCAP3L PCA Compare/Capture Register 3 Low Byte 80C51FX
; ED MD4 Multiplication/Division Register 4 80C517
; EE CCAP4L PCA Compare/Capture Register 4 Low Byte 80C51FX
; EE FIN FIFO In 80C452
; EE MD5 Multiplication/Division Register 5 80C517
;-------------------------------------------------------------------------------
; EF ARCON Arithmetic Control Register 80C517
; EF CIN Command In Register 80C452
; Bits in ARCON ( not bit-adressable ):
; 0 SC0 Shift Counter Bit 0 80C517
; 1 SC1 Shift Counter Bit 1 80C517
; 2 SC2 Shift Counter Bit 2 80C517
; 3 SC3 Shift Counter Bit 3 80C517
; 4 SC4 Shift Counter Bit 4 80C517
; 5 SLR Right Shift Direction Bit 80C517
; 6 MDOV Overflow Flag 80C517
; 7 MDEF Error Flag 80C517
;-------------------------------------------------------------------------------
; F0 B B Register 8051
; Bits in B:
; Bit address Name Function Resident in
; F0 B.0 B Register Data Bit 0 8051
; F1 B.1 B Register Data Bit 1 8051
; F2 B.2 B Register Data Bit 2 8051
; F3 B.3 B Register Data Bit 3 8051
; F4 B.4 B Register Data Bit 4 8051
; F5 B.5 B Register Data Bit 5 8051
; F6 B.6 B Register Data Bit 6 8051
; F7 B.7 B Register Data Bit 7 8051
;-------------------------------------------------------------------------------
; F1
; F2 BCRL1 DMA Byte Count 1 (LOW) 80C152/452
; F2 CML6 Compare Register 6, Low Byte 80C517
; F2 RTASS Real-Time Alarm Subsecond Register 87C530
; F3 BCRH1 DMA Byte Count 1 (HIGH) 80C152/452
; F3 CMH6 Compare Register 6, High Byte 80C517
; F3 RTAS Real-Time Alarm Second Register 00-3B 87C530
; F4 ADRES7 A/D Conversion Result of Channel 7, ACH7 80C51GB
; F4 CML7 Compare Register 7, Low Byte 80C517
; F4 RFIFO Global Serial Channel Receive Buffer 80C152
; F4 RTAM Real-Time Alarm Minute Register 00-3B 87C530
;-------------------------------------------------------------------------------
; F5 CMH7 Compare Register 7, High Byte 80C517
; F5 MYSLOT Global Serial Channel Slot Address 80C152
; F5 RTAH Real-Time Alarm Hour Register 00-17 87C530
; Bits in MYSLOT ( not bit-adressable ):
; 0 SA0 Slot Address Bit 0 80C152
; 1 SA1 Slot Address Bit 1 80C152
; 2 SA2 Slot Address Bit 2 80C152
; 3 SA3 Slot Address Bit 3 80C152
; 4 SA4 Slot Address Bit 4 80C152
; 5 SA5 Slot Address Bit 5 80C152
; 6 DCR Deterministic Collision Resolution 80C152
; 7 DCJ Deterministic Collision Jam 80C152
;-------------------------------------------------------------------------------
; F6 CMEN Compare Enable Register 80C517
; F6 ITHR Input FIFO Threshold 80C452
; Bits in CMEN ( not bit-adressable ):
; 0 CMEN0 Enable Compare Function to CM0 80C517
; 1 CMEN1 Enable Compare Function to CM1 80C517
; 2 CMEN2 Enable Compare Function to CM2 80C517
; 3 CMEN3 Enable Compare Function to CM3 80C517
; 4 CMEN4 Enable Compare Function to CM4 80C517
; 5 CMEN5 Enable Compare Function to CM5 80C517
; 6 CMEN6 Enable Compare Function to CM6 80C517
; 7 CMEN7 Enable Compare Function to CM7 80C517
;---------------------------------------------------------------------------
; F7 CMSEL Compare Input Select 80C517
; F7 OTHR Output FIFO Threshold 80C452
; F7 SEPSTA Serial Expansion Port Status Register 80C51GB
; Bits in CMSEL ( not bit-adressable ):
; 0 CMSEL0 Select CM0 Assigned to Compare Timer 80C517
; 1 CMSEL1 Select CM1 Assigned to Compare Timer 80C517
; 2 CMSEL2 Select CM2 Assigned to Compare Timer 80C517
; 3 CMSEL3 Select CM3 Assigned to Compare Timer 80C517
; 4 CMSEL4 Select CM4 Assigned to Compare Timer 80C517
; 5 CMSEL5 Select CM5 Assigned to Compare Timer 80C517
; 6 CMSEL6 Select CM6 Assigned to Compare Timer 80C517
; 7 CMSEL7 Select CM7 Assigned to Compare Timer 80C517
; Bits in SEPSTA ( not bit-adressable ):
; 0 SEPIF Serial Expansion Port Interrupt Flag 80C51GB
; 1 SEPFNRD SEPDAT Read Attempted During Data Reception 80C51GB
; 2 SEPFNWR Write Attempted During Data Reception 80C51GB
; 3
; 4
; 5
; 6
; 7
;------------------------------------------------------------------------------
; F8 EIP Extended Interrupt Priority 80C310
; F8 IEP Interrupt Enable and Priority 80C452
; F8 IPN1 Interrupt Priority Register 1 80C152
; F8 P5 Port 5 ( Bidirectional ) 80C51GB 80515
; Bits in EIP:
; Bit address Name Function Resident in
; F8 EIP.0 PX2 External Interrupt 2 Priority 80C310
; F9 EIP.1 PX3 External Interrupt 3 Priority 80C310
; FA EIP.2 PX4 External Interrupt 4 Priority 80C310
; FB EIP.3 PX5 External Interrupt 5 Priority 80C310
; FC EIP.4 PWDI Watchdog Interrupt Priority 80C320
; FD EIP.5 PRTCI Real-Time Clock Interrupt Priority 87C530
; FE EIP.6
; FF EIP.7
; Bits in IEP:
; Bit address Name Function Resident in
; F8 IEP.0 EFIFO FIFO Slave Bus Interface Interrupt Enable 80C452
; F9 IEP.1 PDMA1 DMA Channel 1 Interrupt Priority 80C452
; FA IEP.2 PDMA0 DMA Channel 0 Interrupt Priority 80C452
; FB IEP.3 EDMA1 DMA Channel 1 Interrupt Enable 80C452
; FC IEP.4 EDMA0 DMA Channel 0 Interrupt Enable 80C452
; FD IEP.5 PFIFO FIFO Slave Bus Interface Interrupt Priority 80C452
; FE IEP.6
; FF IEP.7
; Bits in IPN1:
; Bit address Name Function Resident in
; F8 IPN1.0 PGSRV GSC Receive Valid Interrupt Priority 80C152
; F9 IPN1.1 PGSRE GSC Receive Error Interrupt Priority 80C152
; FA IPN1.2 PDMA0 DMA Channel 0 Done Interrupt Priority 80C152
; FB IPN1.3 PGSTV GSC Transmit Valid Interrupt Priority 80C152
; FC IPN1.4 PDMA1 DMA Channel 1 Done Interrupt Priority 80C152
; FD IPN1.5 PGSTE GSC Transmit Error Interrupt Priority 80C152
; FE IPN1.6
; FF IPN1.7
; Bits in P5:
; Bit address Name Function Resident in
; F8 P5.0 Parallel I/O Port 5 Bit 0 80C51GB 80515
; F8 P5.0 CCM0 Concurrent Compare 0 80C517
; F9 P5.1 Parallel I/O Port 5 Bit 1 80C51GB 80515
; F9 P5.1 CCM1 Concurrent Compare 1 80C517
; FA P5.2 Parallel I/O Port 5 Bit 2 80C51GB 80515
; FA P5.2 CCM2 Concurrent Compare 2 80C517
; FA P5.2 INT2 External Interrupt 2 80C51GB
; FB P5.3 Parallel I/O Port 5 Bit 3 80C51GB 80515
; FB P5.3 CCM3 Concurrent Compare 2 80C517
; FB P5.3 INT3 External Interrupt 3 80C51GB
; FC P5.4 Parallel I/O Port 5 Bit 4 80C51GB 80515
; FB P5.4 CCM4 Concurrent Compare 2 80C517
; FC P5.4 INT4 External Interrupt 4 80C51GB
; FD P5.5 Parallel I/O Port 5 Bit 5 80C51GB 80515
; FD P5.5 CCM5 Concurrent Compare 2 80C517
; FD P5.5 INT5 External Interrupt 5 80C51GB
; FE P5.6 Parallel I/O Port 5 Bit 6 80C51GB 80515
; FE P5.6 CCM6 Concurrent Compare 6 80C517
; FF P5.7 Parallel I/O Port 5 Bit 7 80C51GB 80515
; FF P5.7 CCM7 Concurrent Compare 7 80C517
;-------------------------------------------------------------------------------
; F9 CH PCA Timer/Counter Register Low Byte 80C51FX
; F9 MODE External Host-FIFO Interface Mode Control 80C452
; F9 RTCC Real-Time Clock Control Register 87C530
; Bits in MODE ( not bit-adressable ):
; 0
; 1
; 2
; 3
; 4 MD4 Configure INTRQ 80C452
; 5 MD5 Configure DRQIN/INTRQIN and DRQOUT/INTRQOUT 80C452
; 6 MD6 Request for Service to External CPU via DMA 80C452
; 7
; Bits in RTCC ( not bit-adressable ):
; 0 RTCE RTC Enable 87C530
; 1 RTCIF RTC Interrupt Flag 87C530
; 2 RTCWE RTC Write Enable 87C530
; 3 RTCRE RTC Read Enable 87C530
; 4 HCE RTC Hour Register Compare Enable 87C530
; 5 MCE RTC Minute Register Compare Enable 87C530
; 6 SCE RTC Second Register Compare Enable 87C530
; 7 SSCE RTC Subsecond Register Compare Enable 87C530
;-------------------------------------------------------------------------------
; FA CCAP0H PCA Compare/Capture Register 0 Low Byte 80C51FX
; FA ORPR Output Read Pointer 80C452
; FA P6 Port 6 ( Bidirectional ) 80C517
; FA RTCSS Real-Time Clock Subsecond Register 87C530
; Bits in P6 ( not bit-adressable ):
; 0 Parallel I/O Port 6 Bit 0 80C517
; 0 nADST External A/D Converter Start 80C517
; 1 Parallel I/O Port 6 Bit 1 80C517
; 1 RXD1 Serial Input Channel 1 80C517
; 2 Parallel I/O Port 6 Bit 2 80C517
; 2 TXD1 Serial Output Channel 1 80C517
; 3 Parallel I/O Port 6 Bit 3 80C517
; 4 Parallel I/O Port 6 Bit 4 80C517
; 5 Parallel I/O Port 6 Bit 5 80C517
; 6 Parallel I/O Port 6 Bit 6 80C517
; 7 Parallel I/O Port 6 Bit 7 80C517
;-------------------------------------------------------------------------------
; FB CCAP1H PCA Compare/Capture Register 1 Low Byte 80C51FX
; FB OTWR Output WriteO Threshold 80C452
; FB RTCS Real-Time Clock Second Register 00-3B 87C530
; FC CCAP2H PCA Compare/Capture Register 2 Low Byte 80C51FX
; FC IMIN Immediate Command In 80C452
; FC RTCM Real-Time Clock Minute Register 00-3B 87C530
;-------------------------------------------------------------------------------
; FD CCAP3H PCA Compare/Capture Register 3 Low Byte 80C51FX
; FD IMOUT Immediate Command Out 80C452
; FD IS0 not user accessable 80C517A
; FD RTCH Real-Time Clock Hour Register 00-17/1-7 87C530
; Bits in RTCH ( not bit-adressable ):
; 0 RTCH0 Real-Time Clock Hours Bit 0 87C530
; 1 RTCH1 Real-Time Clock Hours Bit 1 87C530
; 2 RTCH2 Real-Time Clock Hours Bit 2 87C530
; 3 RTCH3 Real-Time Clock Hours Bit 3 87C530
; 4 RTCH4 Real-Time Clock Hours Bit 4 87C530
; 5 DOW0 Real-Time Clock Day of the Week Bit 0 87C530
; 6 DOW1 Real-Time Clock Day of the Week Bit 1 87C530
; 7 DOW2 Real-Time Clock Day of the Week Bit 2 87C530
;-------------------------------------------------------------------------------
; FE CCAP4H PCA Compare/Capture Register 4 Low Byte 80C51FX
; FE FOUT FIFO Out 80C452
; FE IS1 not user accessable 80C517A
; FE RTCD0 Real-Time Clock Day Register Low Byte 87C530
; FF COUT Command Out DMA Destination Address 80C452
; FF RTCD1 Real-Time Clock Day Register High Byte 87C530
; Ende SFR.D
;
;*******************************************************************************
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