KyteLabs CrossAssemblers - Online User Manual | Last modified: 2005-03-04 (14366) |
Command: AS80C52 <source file> [+|-<options>] Defaults: *.ASM +GLSU +B=0 OPTIONS WITHOUT PARAMETERS: +? Show help page. -L Suppress listing if no errors. -B No object file generated. +M Show macro expansion. +C Show Conditioning. -P No page formatting. -G No multiple code lines. -S No symbols in object file. +H H/L byte sex using DW. -U Force upper-case folding. OPTIONS WITH PARAMETERS: +B=S Generate object file in following format: S=M Motorola, S=I Intel, S=NN binary file for NN K size EPROM. +A=SSSS Assign string SSSS to assembler parameter &A. +D=N Debug mode N=1: Show PC destination address. +R=NN Reduced symbol length NN characters. +T=NN Tabulator steps. +W=NNN Listing characters per line. +X=HHHH Define external symbol with value HHHH. +Z=NNN Listing lines per page.
Byte Name |
Byte Address |
Description | Resident in |
---|---|---|---|
P0 | 80 | Port 0 | All |
SP | 81 | Stack Pointer | All |
DPL | 82 | Data Pointer, Low Byte | All |
DPH | 83 | Data Pointer, High Byte | All |
PCON | 87 | Power Control Register | All |
TCON | 87 | Timer/Counter 0/1 Control Register | All |
TMOD | 89 | Timer/Counter 0/1 Mode Control Register | All |
TL0 | 8A | Timer 0 Register, Low Byte | All |
TL1 | 8B | Timer 1 Register, Low Byte | All |
TH0 | 8C | Timer 0 Register, High Byte | All |
TH1 | 8D | Timer 1 Register, High Byte | All |
P1 | 90 | Port 1 | All |
SCON | 98 | Serial Port Control Register | All |
SBUF | 99 | Serial Data Buffer | All |
P2 | A0 | Port 2 | All |
IE | A8 | Interrupt Enable Register | All |
SADDR | A9 | Serial Address Register | 80C52 |
P3 | B0 | Port 3 | All |
IP | B8 | Interrupt Priority Register | All |
SADEN | B9 | Serial Address Enable Mask Register | 80C52 |
T2CON | C8 | Timer/Counter 2 Control Register | 8052/C52 |
T2MOD | C9 | Timer/Counter 2 Mode Control Register | 80C52 |
RCAP2L | CA | Timer/Counter 2 Reload/Capture Register, Low Byte | 8052/C52 |
RCAP2H | CB | Timer/Counter 2 Reload/Capture Register, High Byte | 8052/C52 |
TL2 | CC | Timer 2 Register, Low Byte | 8052/C52 |
TH2 | CD | Timer 2 Register, High Byte | 8052/C52 |
PSW | D0 | Program Status Word Register | All |
ACC | E0 | Accumulator Register | All |
B | F0 | B Register | All |
Bit Name |
Bit Address |
Description | Register |
---|---|---|---|
88-8F | Timer/Counter Control Register | TCON | |
IT0 | 88 | External Interrupt 0 Type Control Bit | TCON.0 |
IE0 | 89 | External Interrupt 0 Edge Flag | TCON.1 |
IT1 | 8A | External Interrupt 1 Type Control Bit | TCON.2 |
IE1 | 8B | External Interrupt 1 Edge Flag | TCON.3 |
TR0 | 8C | Timer 0 Run Control Bit | TCON.4 |
TF0 | 8D | Timer 0 Overflow Flag | TCON.5 |
TR1 | 8E | Timer 1 Run Control Bit | TCON.6 |
TF1 | 8F | Timer 1 Overflow Flag | TCON.7 |
98-9F | Serial Port Control Register | SCON | |
RI | 98 | Receive Interrupt Flag | SCON.0 |
TI | 99 | Transmit Interrupt Flag | SCON.1 |
RB8 | 9A | Received Serial Bit 8 | SCON.2 |
TB8 | 9B | Transmitted Serial Bit 8 | SCON.3 |
REN | 9C | Receive Enable Bit | SCON.4 |
SM2 | 9D | Serial Mode Specifier Bit 2 | SCON.5 |
SM1 | 9E | Serial Mode Specifier Bit 1 | SCON.6 |
SM0 | 9F | Serial Mode Specifier Bit 0 | SCON.7 |
A8-AF | Interrupt Enable Register | IE | |
EX0 | A8 | External Interrupt 0 Enable Bit | IE.0 |
ET0 | A9 | Timer 0 Interrupt Enable Bit | IE.1 |
EX1 | AA | External Interrupt 1 Enable Bit | IE.2 |
ET1 | AB | Timer 1 Interrupt Enable Bit | IE.3 |
ES | AC | Serial Port Interrupt Enable Bit | IE.4 |
ET2 | AD | Timer 2 Interrupt Enable Bit | IE.5 |
- | AE | (reserved) | IE.6 |
EA | AF | Enable All Interrupts Bit | IE.7 |
B8-BF | Interrupt Priority Register | IP | |
PX0 | B8 | External Interrupt 0 Priority Bit | IP.0 |
PT0 | B9 | Timer 0 Interrupt Priority Bit | IP.1 |
PX1 | BA | External Interrupt 1 Priority Bit | IP.2 |
PT1 | BB | Timer 1 Interrupt Priority Bit | IP.3 |
PS | BC | Serial Port Interrupt Priority Bit | IP.4 |
PT2 | BD | Timer 2 Interrupt Priority Bit | IP.5 |
- | BE | (reserved) | IP.6 |
- | BF | (reserved) | IP.7 |
C8-CF | Timer/Counter 2 Control Register | T2CON | |
CP_RL2 | C8 | Capture/Reload Flag | T2CON.0 |
C_T2 | C9 | Timer or Couter Select Bit | T2CON.1 |
TR2 | CA | Start/Stop Control Bit for Timer 2 | T2CON.2 |
EXEN2 | CB | Timer 2 External Enable Flag | T2CON.3 |
TCLK | CC | Transmit Clock Flag | T2CON.4 |
RCLK | CD | Receive Clock Flag | T2CON.5 |
EXF2 | CE | Timer 2 External Flag | T2CON.6 |
TF2 | CF | Timer 2 Overflow Flag | T2CON.7 |
D0-D8 | Program Status Word Register | PSW | |
P | D0 | Parity Flag | PSW.0 |
F1 | D1 | User Definable Flag 1 | PSW.1 |
OV | D2 | Overflow Flag | PSW.2 |
RS0 | D3 | Register Bank Select Control Bit 0 | PSW.2 |
RS1 | D4 | Register Bank Select Control Bit 1 | PSW.4 |
F0 | D5 | User Flag 0 | PSW.5 |
AC | D6 | Auxiliary Carry Flag | PSW.6 |
CY | D7 | Carry Flag | PSW.7 |
Date (Version#) |
Target | Platform | Remarks |
---|---|---|---|
1999-11-15 (12430.03) |
AS80C52 (8051 Family) |
Mac | First release to the public. Internationalized version based on English language with Preliminary User Manual supplied. |
1999-11-21 (12436.01) |
AS80C52 (8051 Family) |
Mac | Enhanced version supporting Intel Hex object file output. New online user manual provided, now platform independent by using HTML. |
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